The development of the electronic packaging technology is a key to the advancement in performance and the miniaturization of the electronic products, such as computers, calculators, IC cards, etc. In the past twenty yeas, the Dual-In-Line Package (DIP) had played a very important role in the development of more sophisticated technologies for packaging the electronic elements. According to the DIP technology, the lead frame is bonded onto a printed circuit board by means of pins, which are implanted into the plated through holes of the printed circuit board. The bonding is further reinforced by soldering. The DIP technology has a bottleneck, which involves the production technology of the lead frame such that the input/output number of a great density is technically infeasible. In the era of 1980s, the Surface Mount Technology (SMT) was introduced in place of the DIP technology. By using the Surface Mount Technology, the input/output number of a greater density and the production automation are technically feasible. As a result, the Surface Mount Technology is a state-of-the-art technology as far as the electronic packaging technology is concerned. However, as the application of the Surface Mount Technology has reached its peak in the recent past, a new technology known as Multichip Module (MCM) has flourished in the recent years. The importance and the significance of the MCM packaging technology are witnessed by a number of research reports published by researchers around the world, as well as numerous international symposia and seminars held by academicians and technicians. In addition, the MCM packaging technology has made it possible for the electronic industry to realize the further miniaturization of the electronic products.
There are several varieties of the multichip modules, depending on the natures of the substrates, such as MCM-C (ceramic substrate), MCM-P (high molecular substrate), MCM-Si (silicon substrate), and MCM-D (film deposition), etc. On the basis of the bonding technology of the silicon chip and the substrate, the MCM technology can be divided into the wire bonding, the tape automatic bonding (TAB), and the flip chip bonding. The wire bonding and the tape automatic bonding are confined to the arrangement of the space geometry of the bonding point, so that the bonding points on a silicon chip must be located at the periphery of the chip, and thus the number of the bonding points is limited. Due to the limited number of the bonding points, the number of the bonding points on a single chip, TAB may reach 600 or so, or even fewer for wire bonding. However, the flip chip bonding may reach 1600. Such a difference as described above is due to the fact that the bonding points of the flip chip bonding can be designed as matrix, and that the surface area of the chip is fully utilized. The technology was first developed by IBM in the era of 1960s; nevertheless the technology was patented to prevent any further involvement by other members of the electronic industry until recent years.
The flip chip bonding, which is also known as the controlled collapse chip connection, C.sub.4, eliminates the need of the space for wire and lead such that the chip can be directly adhered to the substrate. This technology is called the chip-on-board packaging technology or the bare chip bonding technology, which substantially reduces the need for sealing resin and promotes the input-output or the integration density of the chip as well as the chip density on the substrate to which chips are adhered. A key in the flip chip bonding technology is the solder bumps formed directly on the chip as joints must meet the requirements of the substrate circuit and the chip circuit. The solder bump is an alloy of Pb--Sn and its composition varies depending on the fabrication temperature. The solder bumps are contacted with the bump pad of the substrate by alignment. The chip is bonded onto the substrate by reflow.
The preparation of solder bumps on the chip is attained by physical vapor deposition (PVD) or electroplating, in which a desired pattern of solder bumps is first prepared by forming a patterned mask by lithography before the soldering is brought about by PVD or electroplating. The physical vapor deposition and the electroplating are defective in design in that their deposition growth is slow, and that their batch production process can not be easily automated. In addition, the thermal evaporation of the physical vapor deposition is carried out at a high temperature with a slow growth rate such that the solder bumps so produced on the chip are vulnerable to being melted. The electroplating process is more complicated than the physical vapor deposition in view of the fact that the height of the solder bumps is controlled by the current density distribution, and that the solder bumps have a flat surface which must be further treated by reflow to become an arcuate surface to facilitate the bonding.